The present invention relates to semiconductor memory device manufacturing, and more particularly to methods for forming dual work function high-performance support metal oxide semiconductor field effect transistors (MOSFETs) in an embedded dynamic random access memory (EDRAM) array.
Dual work function devices are becoming increasingly common in CMOS devices to provide enhanced PMOS performance. A transistor consists of a gate, a source, and a drain. In dual work function devices commonly practiced in the art, if the source and drain are doped N+, the polysilicon gate must also be doped n-type. Conversely, if the source and drain are doped P+, the polysilicon gate is doped p-type.
As devices shrink in size, more devices as well as devices of different types can be integrated onto the same substrate to provide electronic systems on a single substrate. These so-called systems on chip (SOC) further enhance performance of electronic products. Now it is possible to provide both high speed logic as well has high density dynamic random access memories (DRAM) on a single substrate.
Most DRAM circuits emphasize circuit density and reduced cost. In contrast, logic circuits emphasize speed. Dual work function logic devices are faster than single work function devices but are more complex to fabricate. In contrast, single work function devices are easier to fabricate and are used with dense memory arrays in conventional DRAMS. Until recently, most DRAMs were fabricated with single work function devices and logic products, such as microprocessors, were fabricated with dual work function devices. Adding dual work function devices to a process flow also adds to the complexity and relative cost of fabricating the SOC. For instance, memory circuits achieve increased density requirements by employing self-aligned contacts (borderless bit line contacts), which are easily implemented in a process having a single type, e.g. typically N+ type, gate work function. A buried-channel type PMOSFET is used in creating DRAMs because it permits a single work function gate conductor, N+, to be used throughout the fabrication process. This lowers the cost of fabricating DRAMs, but at the expense of creating an inferior performing PMOSFET. On the other hand, logic circuits require both P+ and N+ gated MOSFETs in order to achieve the necessary switching speeds. P+ and N+ gate conductor devices are highly desirable for EDRAM products.
EDRAM applications demand both the utmost in high-performance CMOS (complementary metal oxide semiconductor) logic devices and high-density DRAM arrays. High-performance CMOS logic devices require low-resistance gate conductors and source/drain diffusions (salicidation), which drive processes that are costly and difficult to integrate with high-density DRAM processes. For example, salicided gates and source/drain regions greatly complicate the processes for forming array MOSFETs since the array MOSFETs need bitline contacts which are borderless to adjacent wordline conductors. Also, salicided junctions in the array may result in increased current leakage of the memory device.
A DRAM circuit will usually include an array of memory cells interconnected by rows and columns, which are known as wordlines and bitlines, respectively. Reading data from, or writing data to, memory cells is achieved by activating selected wordlines and bitlines. Typically, a DRAM memory cell comprises a MOSFET connected to a capacitor. The capacitor includes gate and diffusion regions which are referred to as either drain or source regions, depending on the operation of the transistor.
There are different types of MOSFETs. A planar MOSFET is a transistor where a surface of the channel region of the transistor is generally parallel to the primary surface of the substrate. A vertical MOSFET is a transistor where a surface of the channel region of the transistor is generally perpendicular to the primary surface of the substrate. A trench MOSFET is a transistor where a surface of the channel region of the transistor is not parallel to the primary surface of the substrate and the channel region lies within the substrate. For a trench MOSFET, the surface of the channel region is usually perpendicular to the primary surface, although this is not required.
Trench capacitors are frequently used with DRAM cells. A trench capacitor is a three-dimensional structure formed into a silicon substrate. It is normally formed by etching trenches of various dimensions into the silicon substrate. Trenches commonly have N+ doped polysilicon as one plate of the capacitor (a storage node). The other plate of the capacitor is formed usually by diffusing N+ dopants out from a dopant source into a portion of the substrate surrounding the lower part of the trench. Between these two plates, a dielectric layer is placed to form the capacitor.
There is a continuing need for more efficient and less costly techniques to fabricate systems on chip. Consider, for example, the processes shown in U.S. Pat. Nos. 6,261,894 and 6,258,659. Both of them show techniques for fabricating embedded memory arrays with logic support areas. In both cases the gates for the wordline in the array and the gates for the logic devices are separately formed. In effect, two separate processes, a memory forming process and a support (logic) process are separately performed on the substrate. While the array is formed, the support is masked and then the array is masked while the support is formed. If one or more steps in the separate processes were combined, the overall cost and complexity of manufacture would be reduced. These complex processes do not use conventional self-aligned contact techniques and include more steps for manufacturing SOC devices.
The present invention relates to processes for the fabricating embedded vertical DRAM cells and dual work function logic gates. In particular, it relates to a novel process for the fabrication of very high-density DRAM and very high-performance support MOSFETs. It overcomes inefficiencies in the prior art by combining certain steps in the DRAM and logic processes. In particular, the invention forms the gates of the wordline in the array and the CMOS logic gates at the same time.
The invention provides a method for forming wordlines in a memory array area and dual function logic gates in a support area on a semiconductor substrate using self-aligned contact techniques. The process steps include forming vertical dram cells in the array area of the substrate in a conventional manner. Any suitable known or later invented DRAM process is sufficient. After the array devices are formed, a top oxide layer covers the array and a gate oxide layer covers the support. Then the substrate is processed to provide the gate layers for the array and the support devices. In one embodiment a layer of undoped polysilicon is deposited over the surface of the substrate and removed from the array area. Next, the array gate material is deposited and removed from over the support area. Then a common gate mask is formed over the entire substrate and, using the common gate mask, the gates for the array the support areas are etched from the underlying layers. The invention uses self-aligned contact techniques and does not require salicided bit lines.
In one embodiment the support area is covered with undoped polysilicon and a hard mask layer of silicon dioxide. The hard mask layer may be deposited or formed by thermal oxidation. The polysilicon and the oxide hard mask are removed from over the array area. Wordline material is deposited over the substrate and a layer of silicon nitride is deposited over the wordline material. Typical wordline materials are tungsten silicide, titanium disilicide or tungsten/tungsten nitride. The wordline material and the silicon nitride layer are removed from over the support area. Then a soft mask material, such as photoresist, is applied to the nitride and oxide layers and is patterned to form a gate mask. Portions of the photoresist are removed to expose the underlying silicon nitride and silicon dioxide layers. The exposed portions are subjected to one or more plasma etches that remove the underlying nitride, oxide, polysilicon and wordline layers to form the gate structures in the array and support areas. There are known etching materials that remove both silicon nitride and silicon dioxide. There are other etching materials that remove polysilicon and W/Wn but are selective with regard to silicon nitride or silicon dioxide. The gate etching stops on the top oxide layer and gate oxide layer of the arrays and support areas, respectively.
The array devices and the support devices of one work function (e.g. N-type) are masked and the other work function devices (e.g. P-type) are implanted to form P+ gate polysilicon and P+ source and drain regions. Then the process is reiterated over the other support devices to form the N+ polysilicon gates and N+ sources and drains. A sidewall oxide spacer layer is formed over the support area and openings are made to define the source and drain regions. The sidewall oxide layer fills the spaces between the wordlines. The support area sources and drains are salicided with a suitable metal, such as cobalt, to increase their electrical conductivity. That saliciding does not affect the array devices. The SOC is completed in a conventional manner by depositing an interlevel dielectric, planarizing the interlevel dielectric, opening vias in the interlevel dielectric to expose surface contact regions, and depositing a conductive layer that fills vias and makes electrical contact with the contact surfaces exposed in the vias.